AMX DESIGN XPRESS V 1.5 - PROGRAMMER GUIDE Guide de l'utilisateur Page 57

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Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 57
UG197 (v1.5) July 22, 2009
Registers
401
2:0
RETRYRAMWRITELATENCY
RW
5:3
RETRYRAMREADLATENCY
RW
17:6
RETRYRAMSIZE
RW
18 Reserved
19 Reserved
20 Reserved
21 Reserved
24:22
TLRAMWRITELATENCY RW
27:25
TLRAMREADLATENCY RW
402
0 Reserved
8:1
TXTSNFTSCOMCLK RW
16:9
TXTSNFTS RW
17 Reserved
20:18
L1EXITLATENCYCOMCLK
RW
23:21
L1EXITLATENCY
RW
26:24
L0SEXITLATENCYCOMCLK
RW
29:27
L0SEXITLATENCY
RW
403
11:0 Reserved
19:12 Reserved
22:20 Reserved
23 Reserved
26:24
LOWPRIORITYVCCOUNT
RW
Table 2-23: Management Control and Status Registers (Continued)
Management
Address (Hex)
MGMTADDR[10:0]
Bit Position Attribute Name
Read Only or
Read Write
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