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10 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block
UG197 (v1.5) July 22, 2009
Preface: About This Guide
R
attributes are all set through the CORE Generator GUI, this appendix is provided as a
reference.
• “Glossary,” defines various terms used in this document.
Additional Documentation
The following documents are also available for download at
http://www.xilinx.com/virtex5
.
• Virtex-5 Family Overview
The features and product selection of the Virtex-5 family are outlined in this overview.
• Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
This data sheet contains the DC and Switching Characteristic specifications for the
Virtex-5 family.
• Virtex-5 FPGA User Guide
Chapters in this guide cover the following topics:
- Clocking Resources
- Clock Management Technology (CMT)
- Phase-Locked Loops (PLLs)
-Block RAM
- Configurable Logic Blocks (CLBs)
-SelectIO™ Resources
- SelectIO Logic Resources
- Advanced SelectIO Logic Resources
• Virtex-5 FPGA RocketIO GTP Transceiver User Guide
This guide describes the RocketIO™ GTP transceivers available in the Virtex-5 LXT
and SXT devices.
• Virtex-5 FPGA RocketIO GTX Transceiver User Guide
This guide describes the RocketIO GTX transceivers available in the TXT and FXT
devices.
• Virtex-5 FPGA Embedded Processor Block in Virtex-5 FPGAs
This reference guide is a description of the embedded processor block available in the
Virtex-5 FXT device.
• Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC User Guide
This guide describes the dedicated Tri-Mode Ethernet Media Access Controller
available in the Virtex-5 LXT, SXT, TXT, and FXT devices.
• Virtex-5 FPGA XtremeDSP Design Considerations User Guide
This guide describes the XtremeDSP™ slice and includes reference designs for using
the DSP48E.
• Virtex-5 FPGA Configuration Guide
This all-encompassing configuration guide includes chapters on configuration
interfaces (serial and SelectMAP), bitstream encryption, Boundary-Scan and JTAG
configuration, reconfiguration techniques, and readback through the SelectMAP and
JTAG interfaces.
- Virtex-5 FPGA 1
- Integrated Endpoint Block 1
- Revision History 3
- VC1*, LOWPRIORITYVCCOUNT 4
- Table of Contents 5
- About This Guide 9
- Additional Documentation 10
- Additional Support Resources 11
- Typographical Conventions 11
- Preface: About This Guide 12
- Block Overview 13
- Memory Requirements 15
- Use Models 15
- Chapter 2 17
- Transaction Layer 18
- Data Link Layer 19
- Physical Layer 19
- Physical Layer Lane Module 20
- Clock Frequency 21
- Integrated 22
- Endpoint Block 22
- Transmit 28
- Channels 29
- Channel Ready 29
- Channel Select 29
- Transmit Framing 29
- Framing Errors 30
- DWORD Enables 30
- Transmit Handshake 30
- UG197_c2_04_030607 31
- Receive Framing 32
- Receive Handshake 32
- UG197_c2_06_111906 34
- Management Interface 37
- UG197_c2_08_082406 38
- Block RAM Interface 40
- RX and TX Buffer Capacity 41
- Retry Buffer Size 41
- Transceiver Interface 42
- Power Management Interface 45
- Registers 53
- Table 2-19: MSI Registers 55
- Reserved Registers 56
- Chapter 3 63
- Chapter 4 65
- Configuration Requests 66
- Transaction Ordering 67
- Interrupt Handling 68
- INTERRUPTDISABLE output: 69
- Error Detection 70
- Error Reporting 74
- Message Tags 76
- Phantom Function Support 76
- Lane Width 77
- Lane Reversal 77
- Workaround 78
- Appendix A 91
- TOTALCREDITS attributes are 92
- Initial Flow Control Credits 93
- Extended Capabilities 94
- The offset to the next PCI 105
- Contains the offset of 105
- UG197 (v1.5) July 22, 2009 108
- Glossary 109
- Function 112
- Hot plug 112
- Hot swap 112
- Isochronous data transfer 112
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