AMX DESIGN XPRESS V 1.5 - PROGRAMMER GUIDE Guide de l'utilisateur Page 1

RVirtex-5 FPGAIntegrated Endpoint Block for PCI Express DesignsUser GuideUG197 (v1.5) July 22, 2009

10 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Preface: About This GuideRattributes are all set through the CORE G

100 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Appendix A: Integrated Endpoint Block AttributesRBAR1ADDRWIDTHInte

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 101UG197 (v1.5) July 22, 2009Integrated Endpoint Block AttributesRBAR5PREFETCHABLEBoolean Speci

102 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Appendix A: Integrated Endpoint Block AttributesRXPDEVICEPORTTYPE4

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 103UG197 (v1.5) July 22, 2009Integrated Endpoint Block AttributesRPMCAPABILITYDSIBoolean Device

104 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Appendix A: Integrated Endpoint Block AttributesRMSICAPABILITYMULT

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 105UG197 (v1.5) July 22, 2009Integrated Endpoint Block AttributesRLINKSTATUSSLOTCLOCKCONFIGBool

106 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Appendix A: Integrated Endpoint Block AttributesRPBCAPABILITYDW0DA

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 107UG197 (v1.5) July 22, 2009Integrated Endpoint Block AttributesRAERBASEPTR12-bit Hex Location

108 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Appendix A: Integrated Endpoint Block AttributesR

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 109UG197 (v1.5) July 22, 2009RGlossaryClick on a letter, or scroll down to view the entire glos

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 11UG197 (v1.5) July 22, 2009Additional Support ResourcesR• Virtex-5 FPGA System Monitor User Gu

110 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009RBBARBase Address Register.BeatA clock cycle where both the source

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 111UG197 (v1.5) July 22, 2009RDData Link LayerThe middle layer of the PCI Express architecture,

112 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009RFunctionA logical function corresponding to a PCI function config

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 113UG197 (v1.5) July 22, 2009RLLaneA set of differentially driven signal lines, one for each di

114 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009ROOrdered setThe sequences of multiples of four characters startin

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 115UG197 (v1.5) July 22, 2009RSSidebandA signal that is implemented with its own wire. Communic

116 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Rmultiple virtual channels. There is no correspondence between the

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 117UG197 (v1.5) July 22, 2009AACTIVELANESIN attribute 24, 58, 77, 98AERBASEPTR attribute 94,

118 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009RL0MACRXL0SSTATE port 45L0MSIENABLE0 port 50L0MSIREQUEST0 bus 5

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 119UG197 (v1.5) July 22, 2009RNext Pointer register 55PPARITYERRORRESPONSE port 52PBBASEPTR a

12 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Preface: About This GuideR

120 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009RTTLRAMREADLATENCY attribute 57, 98TLRAMREADLATENCY port 32TLRAM

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 13UG197 (v1.5) July 22, 2009RChapter 1Virtex-5 FPGA Integrated Endpoint Block OverviewSummaryTh

14 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 1: Virtex-5 FPGA Integrated Endpoint Block OverviewRVirtex-

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 15UG197 (v1.5) July 22, 2009Memory RequirementsRMemory RequirementsThere are three buffers that

16 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 1: Virtex-5 FPGA Integrated Endpoint Block OverviewR

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 17UG197 (v1.5) July 22, 2009RChapter 2Integrated Endpoint Block FunctionalitySummaryThis chapte

18 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRTransaction Laye

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 19UG197 (v1.5) July 22, 2009Architecture OverviewRThe PCI Express protocol supports four types

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com UG197 (v1.5) July 22, 2009Xilinx is disclosing this user guide, manual, release note, and/or sp

20 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityR• Link initializ

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 21UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRVirt

22 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRWhen the frequen

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 23UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRRese

24 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRDuring FPGA conf

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 25UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRThe

26 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRCRMURSTNInput co

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 27UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRCRMD

28 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRTransaction Laye

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 29UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRChan

UG197 (v1.5) July 22, 2009 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockRevision HistoryThe following table shows the revision history for th

30 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRFraming ErrorsTh

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 31UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRAfte

32 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRReceive FramingT

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 33UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRWhen

34 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRIf LLKRXDSTREQN

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 35UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRLLKT

36 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRLLKRXSRCRDYNOutp

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 37UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRMana

38 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRperforming the f

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 39UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRMGMT

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com UG197 (v1.5) July 22, 200909/23/08 1.4 • Removed references to Virtual Channel 1 (VC1) and mult

40 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRBlock RAM Interf

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 41UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRA pi

42 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRPortsTable 2-11,

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 43UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRRock

44 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRPIPETXDATAKLnOut

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 45UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRPowe

46 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRConfiguration an

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 47UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRL0MA

48 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRL0DLUPDOWN[7:0]O

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 49UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRL0SE

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 5UG197 (v1.5) July 22, 2009Revision History . . . . . . . . . . . . . . . . . . . . . . . . . .

50 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRL0SETCOMPLETIONT

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 51UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRL0ST

52 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRBUSMASTERENABLEO

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 53UG197 (v1.5) July 22, 2009RegistersRRegistersThe tables in this section describe the register

54 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRPower Management

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 55UG197 (v1.5) July 22, 2009RegistersRMessage Signaled Interrupt (MSI) Capability StructureTabl

56 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRReserved Registe

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 57UG197 (v1.5) July 22, 2009RegistersR4012:0 RETRYRAMWRITELATENCYRW5:3 RETRYRAMREADLATENCYRW17:

58 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityR4040 Reserved3:1

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 59UG197 (v1.5) July 22, 2009RegistersR4090 BAR0ADDRWIDTHRW1 BAR1ADDRWIDTHRW2 BAR2ADDRWIDTHRW3 B

6 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009RConfiguration and Status Interface . . . . . . . . . . . . . . . .

60 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityR41012:0 Reserved

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 61UG197 (v1.5) July 22, 2009RegistersR41812:0 VC0TXFIFOLIMITC RW13 Reserved26:14 VC0TXFIFOLIM

62 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityR

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 63UG197 (v1.5) July 22, 2009RChapter 3Designing with the Endpoint Block Plus WrapperUsers who a

64 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 3: Designing with the Endpoint Block Plus WrapperR

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 65UG197 (v1.5) July 22, 2009RChapter 4Integrated Endpoint Block OperationSummaryThis chapter pr

66 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 4: Integrated Endpoint Block OperationRhas transmitted. Eve

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 67UG197 (v1.5) July 22, 2009Transaction OrderingRTransaction OrderingThe PCI Express Base Speci

68 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 4: Integrated Endpoint Block OperationRapplied to determine

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 69UG197 (v1.5) July 22, 2009Interrupt HandlingRDisable bit in the PCI Command register is set t

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 7UG197 (v1.5) July 22, 2009RACK Ignored When Followed by IDLE Ordered Set . . . . . . . . . . .

70 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 4: Integrated Endpoint Block OperationRError DetectionThe P

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 71UG197 (v1.5) July 22, 2009Error DetectionRThat configuration requests obey the following rest

72 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 4: Integrated Endpoint Block OperationRThat Memory Read Req

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 73UG197 (v1.5) July 22, 2009Error DetectionRThat the TC associated with each TLP is mapped to a

74 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 4: Integrated Endpoint Block OperationRError ReportingWhile

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 75UG197 (v1.5) July 22, 2009Error ReportingRTable 4-3: Error Reporting with Integrated Endpoint

76 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 4: Integrated Endpoint Block OperationRTable 4-4 summarizes

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 77UG197 (v1.5) July 22, 2009Lane WidthRLane WidthThe maximum number of lanes supported by a des

78 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 4: Integrated Endpoint Block OperationRKnown RestrictionsTh

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 79UG197 (v1.5) July 22, 2009Known RestrictionsR64-Packet Threshold for Completion Streaming on

8 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009R

80 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 4: Integrated Endpoint Block OperationRHowever, if the post

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 81UG197 (v1.5) July 22, 2009Known RestrictionsRInvalid Cycles in LLKRXPREFERREDTYPE SignalDue t

82 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 4: Integrated Endpoint Block OperationRLink Retrain Due to

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 83UG197 (v1.5) July 22, 2009Known RestrictionsRWorkaroundTo avoid the issues listed, the user n

84 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 4: Integrated Endpoint Block OperationRAccess to Unimplemen

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 85UG197 (v1.5) July 22, 2009Known RestrictionsRWorkaroundThe user can work around this issue by

86 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 4: Integrated Endpoint Block OperationRCredit Leak When Tra

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 87UG197 (v1.5) July 22, 2009Known RestrictionsRReceipt of Back-to-Back ACK DLLPsWhenever ACKs a

88 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 4: Integrated Endpoint Block OperationR

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 89UG197 (v1.5) July 22, 2009RChapter 5Simulating with the Integrated Endpoint BlockFor simulati

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 9UG197 (v1.5) July 22, 2009RPrefaceAbout This GuideThis guide serves as a technical reference d

90 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 5: Simulating with the Integrated Endpoint BlockR

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 91UG197 (v1.5) July 22, 2009RAppendix AIntegrated Endpoint Block AttributesSummaryThis appendix

92 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Appendix A: Integrated Endpoint Block AttributesRinterspersed with

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 93UG197 (v1.5) July 22, 2009Initial Flow Control CreditsR The write latency attribute settings

94 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Appendix A: Integrated Endpoint Block AttributesR• Infinite Complet

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 95UG197 (v1.5) July 22, 2009Extended CapabilitiesRTwo linked lists are defined. The method used

96 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Appendix A: Integrated Endpoint Block AttributesRIntegrated Endpoin

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 97UG197 (v1.5) July 22, 2009Integrated Endpoint Block AttributesRVC0RXFIFOBASEP13-bit Hex Base

98 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Appendix A: Integrated Endpoint Block AttributesRACTIVELANESIN8-bit

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 99UG197 (v1.5) July 22, 2009Integrated Endpoint Block AttributesRL0SEXITLATENCYCOMCLKInteger Se