AMX DESIGN XPRESS V 1.5 - PROGRAMMER GUIDE Guide de l'utilisateur Page 269
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- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Chapter 17: Testbench and Design Example 17–47
BFM Procedures and Functions
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
msi_poll Procedure
The
msi_poll
procedure tracks MSI completion from the Endpoint.
dma_set_msi Procedure
The
dma_set_msi
procedure sets PCI Express native MSI for the DMA read or the
DMA write.
Table 17–62. msi_poll Procedure
Location altpcietb_bfm_driver_rp.v
Syntax
msi_poll(max_number_of_msi,msi_address,msi_expected_dmawr,msi_expected_dmard,dma_wri
te,dma_read)
Arguments
max_number_of_msi
Specifies the number of MSI interrupts to wait for.
msi_address
The shared memory location to which the MSI messages will be written.
msi_expected_dmawr
When
dma_write
is set, this specifies the expected MSI data value for the
write DMA interrupts which is set by the
dma_set_msi
procedure.
msi_expected_dmard
When the
dma_read
is set, this specifies the expected MSI data value for the
read DMA interrupts which is set by the
dma_set_msi
procedure.
Dma_write
When set, poll for MSI from the DMA write module.
Dma_read
When set, poll for MSI from the DMA read module.
Table 17–63. dma_set_msi Procedure
Location altpcietb_bfm_driver_rp.v
Syntax
dma_set_msi(bar_table, bar_num, bus_num, dev_num, fun_num, direction, msi_address,
msi_data, msi_number, msi_traffic_class, multi_message_enable, msi_expected)
Arguments
bar_table
Address of the Endpoint
bar_table
structure in BFM shared memory.
bar_num
BAR number to analyze.
Bus_num
Set configuration bus number.
dev_num
Set configuration device number.
Fun_num
Set configuration function number.
Direction
When 0 the direction is read.
When 1 the direction is write.
msi_address
Specifies the location in shared memory where the MSI message data
will be stored.
msi_data
The 16-bit message data that will be stored when an MSI message is
sent. The lower bits of the message data will be modified with the
message number as per the PCI specifications.
Msi_number
Returns the MSI number to be used for these interrupts.
Msi_traffic_class
Returns the MSI traffic class value.
Multi_message_enable
Returns the MSI multi message enable status.
msi_expected
Returns the expected MSI data value, which is
msi_data
modified by the
msi_number
chosen.
- User Guide 1
- Contents 3
- Chapter 7. IP Core Interfaces 4
- Chapter 9. Reset and Clocks 5
- Chapter 18. Debugging 8
- 1. Datasheet 9
- 1–2 Chapter 1: Datasheet 10
- Features 10
- Notes to Table 1–2: 11
- Release Information 12
- Device Family Support 12
- Configurations 12
- Debug Features 13
- IP Core Verification 14
- Recommended Speed Grades 15
- 1–8 Chapter 1: Datasheet 16
- Hard IP for PCI Express 17
- Qsys Design Flow 25
- Generating the Testbench 26
- Simulating the Example Design 27
- Modifying the Example Design 34
- Running Qsys 36
- Table 3–5 38
- On Chip r 40
- Direct BFM’s shared memory 47
- {*reconfig_xcvr_clk*} 50
- Compiling the Design 51
- Programming a Device 51
- System Settings 54
- Port Functions 55
- Error Reporting 57
- 31 19 18 17 16 15 14 58
- Power Management 59
- Legacy Interrupt 63
- Base Address Registers 66
- PCI Express/PCI Capabilities 67
- Header 68
- 6. IP Core Architecture 75
- Avalon-ST Interface 77
- RX Datapath 77
- TX Datapath 77
- Altera FPGA 77
- Clocks and Reset 78
- Interrupts 79
- Transaction Layer 79
- Protocol Layers 80
- Configuration Space 81
- Data Link Layer 81
- Figure 6–4. Data Link Layer 82
- Physical Layer 83
- Figure 6–5. Physical Layer 84
- Multi-Function Support 86
- PCI Express Avalon-MM Bridge 86
- Avalon-MM Bridge TLPs 88
- Figure 6–9. Poor Address Map 93
- RX Block 97
- Avalon-MM RX Master Block 97
- TX Block 98
- Interrupt Handler Block 98
- 7. IP Core Interfaces 99
- Note to Table 7–1: 100
- RX Port 102
- Avalon-ST RX Interface 104
- Note to Figure 7–8: 109
- Avalon-ST TX Interface 114
- Note to Table 7–4: 117
- ECRC Forwarding 122
- Clock Signals 122
- Reset Signals 123
- and the LTSSM L0 state 125
- ECC Error Signals 126
- Interrupts for Endpoints 126
- Interrupts for Root Ports 127
- Completion Side Band Signals 127
- Specification, Rev. 2.1 129
- D E F 0 1 2 3 132
- Notes to Table 7–12: 133
- LMI Signals 137
- LMI Read Operation 138
- LMI Write Operation 138
- Power Management Signals 139
- (Full-Featured Qsys) 141
- Completer-Only Single DWord 142
- RX Avalon-MM Master Signals 144
- Transceiver Reconfiguration 146
- Serial Interface Signals 146
- PIPE Interface Signals 150
- Test Signals 153
- Notes to Table 7–26: 154
- 8. Register Descriptions 155
- Note to Table 8–2: 156
- Note to Table 8–3: 157
- Note to Table 8–4: 157
- Note to Table 8–5: 157
- Note to Table 8–6: 158
- Note to Table 8–7: 158
- Note to Table 8–8: 159
- s and wait 162
- PCI Express Mailbox Registers 167
- Note to Table 8–30: 168
- Root Port TLP Data Registers 170
- Sending a TLP 173
- Receiving a Completion TLP 173
- Endpoints 174
- Avalon-MM Mailbox Registers 175
- Spec 2.1 176
- 9. Reset and Clocks 181
- Example Design 182
- 127 cycles 184
- 300 PPM 185
- Transceiver Clock Signals 186
- Supported Message Types 189
- Notes to Table 10–1: 191
- Receive Buffer Reordering 192
- Notes to Table 10–2: 193
- MSI Interrupts 195
- 11–2 Chapter 11: Interrupts 196
- Note to Figure 11–4: 197
- Legacy Interrupts 198
- Application Layer 199
- 11–6 Chapter 11: Interrupts 200
- MSI/MSI-X Support 201
- Qsys System 202
- 12. Optional Features 203
- ECRC on the RX Path 204
- ECRC on the TX Path 205
- 13. Flow Control 207
- 13–2 Chapter 13: Flow Control 208
- Throughput of Posted Writes 208
- Chapter 13: Flow Control 13–3 209
- 13–4 Chapter 13: Flow Control 210
- 14. Error Handling 211
- Physical Layer Errors 212
- Data Link Layer Errors 212
- Transaction Layer Errors 213
- s limit 214
- Note to Table 14–4: 215
- Figure 15–2 218
- Core User Guide 219
- 16. SDC Timing Constraints 221
- Endpoint Testbench 224
- Root Port Testbench 225
- Chaining DMA Design Examples 226
- Root Complex 227
- Chaining DMA 227
- Hard IP for 227
- PCI Express 227
- Note to Table 17–2: 232
- Note to Table 17–4: 233
- Test Driver Module 236
- DMA Write Cycles 237
- DMA Read Cycles 239
- Root Port Design Example 240
- Root Port 241
- Variation 241
- (variation_name.v) 241
- Root Port BFM 242
- BFM Memory Map 244
- Figure 17–6 248
- BFM Read and Write Procedures 250
- BFM Procedures and Functions 251
- BFM Configuration Procedures 256
- Shared Memory Constants 257
- 18. Debugging 271
- 18–2 Chapter 18: Debugging 272
- Link Training 272
- Chapter 18: Debugging 18–3 273
- 18–4 Chapter 18: Debugging 274
- Chapter 18: Debugging 18–5 275
- Setting Up Simulation 276
- Chapter 18: Debugging 18–7 277
- Use Third-Party PCIe Analyzer 278
- BIOS Enumeration Issues 278
- Notes to Table A–7: 280
- Chapter : A–3 281
- Notes to Table A–16: 282
- Additional Information 283
- Info–2 Revision History 284
- How to Contact Altera 285
- Typographic Conventions 286
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